Services

“Driving innovation with end-to-end design solutions, empowering competitive services with precision and excellence.”

Design Service Solution

From RTL to GDSII — Scalable, Advanced Design Services.
NBIV enables global clients with optimized design flows, high-performance silicon, and deep domain expertise across 3nm to legacy nodes.
“Engineering team working on semiconductor design flow”

Creative Path

Design Service Flow Overview​

RTL or Netlist Handoff: We accept RTL or gate-level netlist designs from customers. Our implementation process begins with

• RTL/Netlist sanity checks
• Design rule checks
• Timing, signal integrity, and thermal analysis
• Scan insertion and error correction
• Final database delivery for tape-out

Logic Synthesis & Logic Equivalence Check

• Library and netlist integrity checks
• Constraint and sanity validation
• Early engagement for PPA (Performance, Power, Area) optimization
• Physical-aware synthesis methodology
• Formal equivalence checking

Low Power Design Solutions

• Low-power architecture planning
• Power domain partitioning and UPF integration
• Clock gating and multi-voltage optimization

Design for Testability (DFT)

• Scan insertion and ATPG pattern generation
• Memory BIST and logic BIST
• At-speed test planning
• DFT architecture and constraints development

Physical Design

• Early power and floor planning
• Chip size estimation and optimization
• Clock Tree Synthesis (custom H-tree / SPINE topology)
• Routing, timing closure, and hold/fix optimization
• Signal integrity (SI) and power analysis (IR/EM)
• Delivered by our experienced team, optimized for advanced process nodes (5nm, 4nm and beyond)

Signoff & Tape-Out

• Static Timing Analysis (STA)
• Power integrity (IR drop, EM) and Signal Integrity (SI) checks)
• Formal DRC/LVS verification)
• GDSII generation and foundry handoff)
• Tape-out support with OSAT interface coordination

Custom Layout Solution

Innovative VLSI solutions, bridging quality and expertise to redefine industry standards and power the future of technology.

At NBIV, we deliver high-quality and reliable custom layout design services for analog, mixed-signal, and digital libraries. With a strong foundation in VLSI layout, library development, and IP integration, we serve key sectors including automotive, AI, and high-performance computing (HPC).
Our solutions are tailored to customer specifications and designed to exceed industry standards, supporting process technologies from 180nm down to 3nm.

Custom Layout Capabilities

Analog IP Portfolio

Custom Layout Design Profile

Custom Layout Capabilities

Core Services
  • Schematic topology and detailed layout specification
  • Circuit-to-layout implementation
  • Library development and characterization
  • IP-level integration and validation
Library Design Capabilities

We support the development of a broad range of cell and IP libraries:

  • I/O Libraries
  • Standard Cell Libraries (conventional & tap-less)
  • High-Speed Interfaces
  • Power Management Libraries:
    • Power switch, PSW controller, level shifter
  • Reliability-Aware Designs:
    • EM/ESD protection, aging & Monte Carlo simulations

Analog IP Portfolio

We offer layout implementation for analog IPs including

We offer layout implementation for analog IPs including:
• PLL, ADC, LVDS, USB, Tribird,
• Voltage droop sensors, Temperature sensors
• Custom analog macros with LPE & post-layout simulation focus

Custom Layout Design Profile

Design Expertise
  • LPE-aware layout with guard rings, matched devices
  • Dummy insertion and resistance optimization for post-layout performance
  • EMIR compliance and thermal-aware layout
Product Experience
  • Standard cell libraries
  • GPIO, SP RAM, DP RAM
  • PLL, LVDS, USB, Tribird
Verification Coverage/span>
  • Physical Verification (PV): DRC, LVS, ERC, Antenna
  • EMIR checks on sensitive paths
  • RC extraction on critical nets for timing/performance
  • Context-aware extraction (standalone, 3D, full-chip)
Deliverables
  • GDS, CDL, SPEF, LEF
  • Complete data package for integration and tape-out
  • Full library characterization & LibQA support

End-to-End HR Operations for Customer Projects

Systematic – Modular – Reusable

NBIV provides full-cycle team setup and management for customer projects — from recruitment and onboarding to HR operations and performance tracking
We handle:
  • Engineer sourcing (RTL, DV, PD, etc.)
  • Training & integration with your workflow
  • Workspace & tool setup
  • Payroll, tax, and compliance in Vietnam
  • Daily supervision & progress reporting
  • A turnkey engineering team, managed for you.
Design Verification Capabilities

Verification Levels

  • IP-Level Verification: Independent functional IP validation
  • SoC-Level Verification: Integration-level simulation & validation
  • Function-level simulation with selective pre-GLS setup
  • Post-GLS verification environment readiness

UVM-Based Environment

  • Modern UVM testbench infrastructure
  • Parameterized and reusable verification components
  • Assertion-based verification and functional coverage
  • Seamless integration with RTL/DFT/backend teams

Protocol & Interface Coverage

We have expertise in verifying IPs and interfaces including:

  • USB 2.0 / USB 3.0
  • PCIe (Gen3 / Gen4)
  • AMBA interfaces: APB, AHB, AXI
  • I2C / I3C, DSI / CSI2
  • UFS / UniPro, VByOne
  • PHY interface for PCIe Gen4
  • ADC IPs and memory-mapped peripherals
  • DFT Compiler integration test environments
Coverage-Driven Verification
  • Code coverage: Statement, branch, expression
  • Toggle coverage: Signal-level toggle rates
  • Functional coverage: Requirement-driven coverage points
  • Continuous tracking via industry-standard simulators and coverage tools
“With NBIV, clients can trust reliable delivery, performance optimization, and cost-effective outcomes.”

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